PCF85263ATSLASHA datasheet(57/92 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus

The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes

the time. In this state, the prescaler can be cleared with the CPR command in the Resets

Remark: The output of clock frequencies is not affected.

The time circuits can then be set and do not increment until the STOP bit is released.

The stop acts on the 8.192 kHz signal. And because the I2C-bus or TS pin input is

asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 33).

aaa-004417

0 µs to 122 µs

8192 Hz

stop released

Figure 33. STOP release timing

The first increment of the time circuits is between 0 s and 122 μs after STOP is released.

The flow for accurately setting the time in RTC mode is:

• start an I2C access at register 2Eh

• set STOP bit

• send CPR instruction

• address counter rolls over to address 00h

• set time (100th seconds, seconds to years)

• end I2C access

• wait for external time reference to indicate that time counting should start

• start an I2C access at register 2Eh

• clear STOP bit (time starts counting from now)

• end I2C access

The flow for resetting time in stop-watch mode is:

• start an I2C access at register 2Eh

• set STOP bit

• send CPR instruction

• address counter will roll over to address 00h

• set time to 000000:00:00.00

• end I2C access

8 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs. The two

lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy. Both data and clock lines remain HIGH when the bus is not

busy. The PCF85263A acts as a slave receiver when being written to and as a slave

transmitter when being read from.

Remark: When on VBAT power, the interface is not accessible.

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 1 February 2021

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