Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07AE.3AD1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
PWMDIV
USEPWMDIV
reserved
USESYSDIV
SYSDIV
ACG
reserved
RO
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Type
0
1
1
1
0
1
0
1
1
1
1
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MOSCDIS
IOSCDIS
reserved
OSCSRC
XTAL
reserved
BYPASS
reserved
PWRDN
reserved
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
RO
Type
1
0
0
0
1
0
1
1
0
1
0
1
1
1
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:28
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
0
R/W
ACG
27
73
June 14, 2007
Luminary Micro Confidential-Advance Product Information
LM3S6950 Microcontroller
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
