D820LP SPECIFICATION UPDATE

10

2.

Change to Description of Section 1.6.4, Real-Time Clock, CMOS

SRAM, and Battery

The note in section 1.6.4 will be changed in its entirety as follows:

If the battery and AC power fail, custom defaults if previously saved, will be

loaded into CMOS RAM at power-on.

The recommended method of accessing the date in systems with D820LP boards

is indirectly from the Real-Time Clock (RTC) via the BIOS. The BIOS on

D820LP boards contains a century checking and maintenance feature. This

feature checks the two least significant digits of the year stored in the RTC

during each BIOS request (INT 1Ah) to read the date and, if less than 80 (i.e.,

1980 is the first year supported by the PC), updates the century byte to 20. This

feature enables operating systems and applications using the BIOS date/time

services to reliably manipulate the year as a four-digit value.

3.

Change to Description of Section 1.5.2, Memory Features

Section 1.5.2, Memory Features will be changed in its entirety as follows:

1.5.2

Memory Features

as an electrically pipelined serial bus (16 data bits in width) with uniform impedance of

28 ohms and single-ended termination. This Rambus channel is capable of providing a

processor-to-memory bandwidth up to 1.6 GB/sec.

The board supports the following memory features:

• Up to two 2.5 V, 184-pin, RIMM* modules

• 512 MB maximum onboard capacity using 128 or 144 Mbit technology

• Single or double-sided RIMM modules

• Serial Presence Detect (SPD) memory only

• Non-ECC memory with 16-bit components (128 Mbit technology)

• ECC memory with 18-bit components (144 Mbit technology)