M29F100BT datasheet(5/22 Pages) STMICROELECTRONICS

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M29F100BT, M29F100BB

Table 5. Bus Operations, BYTE = VIL

Note: X = VIL or VIH.

Table 6. Bus Operations, BYTE = VIH

Note: X = VIL or VIH.

Operation

Address Inputs

DQ15A–1, A0-A15

Data Inputs/Outpu ts

DQ14-DQ8

DQ7-DQ0

Bus Read

VIL

VIH

Cell Address

Hi-Z

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Hi-Z

Data Input

Output Disable

VIH

Hi-Z

Standby

VIH

Hi-Z

Read Manufacturer

Code

VIL

VIH

A0 = VIL,A1 = VIL,A9 = VID,

Others VIL or VIH

Hi-Z

20h

Read Device Code

VIL

VIH

A0 = VIH,A1 = VIL,A9 = VID,

Others VIL or VIH

Hi-Z

D0h (M29F100BT)

D1h (M29F100BB)

Operation

Address Inputs

A0-A15

Data Inputs/Outpu ts

DQ15A–1, DQ14-DQ0

Bus Read

VIL

VIH

Cell Address

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Data Input

Output Disable

VIH

Hi-Z

Standby

VIH

Hi-Z

Read Manufacturer

Code

VIL

VIH

A0 = VIL,A1 = VIL,A9 = VID,

Others VIL or VIH

0020h

Read Device Code

VIL

VIH

A0 = VIH,A1 = VIL,A9 = VID,

Others VIL or VIH

00D0h (M29F100BT)

00D1h (M29F100BB)

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 5 and 6, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs/Outputs will output the

value, see Figure 8, Read Mode AC Waveforms,

and Table 14, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, VIH, during the whole Bus

Write operation. See Figures 9 and 10, Write AC

Waveforms, and Tables 15 and 16, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

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