PDSP1601/PDSP1601A

11

ALU Control Instructions

Function

The BFP flag is programmed to activate when an ALU operation causes an overflow of the

16 bit number range. This flag is logically the exclusive-or of the carry into and out of the

MSB of the ALU. For the most significant Byte this flag indicates that the result of an

arithmetic two's complement operation has overflowed into the sign bit. The output of the

ALU is forced to zero for the duration of this instruction.

The BFP flag is programmed to activate when an ALU operation comes within a factor of

two of causing an overflow of the 16 bit number range. For the most significant Byte this

flag indicates that the result of an arithmetic two's complement operation is within a factor

of two of overflowing into the sign bit. The output of the ALU is forced to zero for the duration

of this instruction.

The BFP flag is programmed to activate when an ALU operation comes within a factor of

four of causing an overflow of the 16 bit number range. For the most significant Byte this

flag indicates that the result of an arithmetic two's complement operation is within a factor

of four of overflowing into the sign bit. The output of the ALU is forced to zero for the duration

of this instruction.

The BFP flag is programmed to activate when an ALU operation causes a result of zero.

The output of the ALU is forced to zero for the duration of this instruction. During the

execution of this instruction the BFP flag will become active.

The ALU will output the binary value 0000000000000001, the MSB on the left.

The ALU will output the binary value 0000000011111111, the MSB on the left.

The ALU will output the binary value 0000000000001111, the MSB on the left.

The ALU will output the binary value 0101010101010101, the MSB on the left.

Op Code

<18>

<19>

<1A>

<1B>

<1C>

<1D>

<1E>

<1F>

Mnemonic

SBFOV

SBFU1

SBFU2

SBFZE

OPONE

OPBYT

OPNIB

OPALT

Barrel Shifter Instructions

Function

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number present in the SV register. The LSBs are dicarded,

and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number present in the SV register. The LSBs are dicarded, and

the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is rotated to the right by the number of places indicated

by the magnitude of the four bit number present in the SV register. The LSBs that exit the

16 bit field to the right, reappear in the vacant MSBs on the left.

The 16 bit input to the Barrel Shifter is rotated to the left by the number of places indicated

by the magnitude of the four bit number present in the SV register. The LSBs that exit the

16 bit field to the right, reappear in the vacant MSBs on the right.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R1 register. The LSBs are

discarded, and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number resident within the R1 register. The LSBs are discarded,

and the vacant LSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R2 register. The LSBs are

discarded, and the vacant MSBs are filled with zeros.

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number resident within the R2 register. The LSBs are discarded,

and the vacant LSBs are filled with zeros.

Op Code

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

Mnemonic

LSRSV

LSLSV

BSRSV

BSLSV

LSRR1

LSLR1

LSRR2

LSLR2