PDSP16256A datasheet(12/24 Pages) MITEL

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PDSP16256

system contains a microprocessor they can be individually

transferred from a remote master under software control. In

any mode the system clock must be present and stable during

the transfer, and the addressing scheme is such that the least

significant address specifies the coefficient applied to the first

multiplier seen by incoming data.

The addresses used during the load operation are those

illustrated in Fig. 15. The Control Register is loaded when CCS

is high. In byte mode address A0 is used to select the portion

of control register loaded, otherwise the address bits are

redundant. When an EPROM is used to provide coefficients,

this redundancy causes the number of locations needed for

any device to be double that for the coefficients alone.

AUTO EPROM LOAD

When EPROM is tied low, the PDSP16256 assumes the

role of a master device in the system and controls the loading

of coefficients from an external EPROM, see Fig.15. A load

sequence commences when the RES input goes high, and will

continue until every coefficient has been loaded. BUSY goes

high to indicate that a load sequence is occurring and the filter

output is invalid. The device will not commence a filter operation

until the FEN edge is received after BUSY has gone low. This

requirement can be avoided if FRUN is tied high.

The address bus pins become outputs on the Master

device, and produce a new address every four system clock

periods. This four clock interval, minus output delays and the

data set up time, defines the available EPROM access time.

The coefficients are always loaded as bytes. The state of

the BYTE pin on the master device is ignored. This ar-

rangement also allows the eight most significant coefficient bus

pins (C15:8) to be used for other purposes as described later.

Since the 16-bit coefficients are loaded in two bytes the A0 pin

specifies the required byte. The maximum number of stored

coefficients is 128, eight address outputs are therefore pro-

vided for the EPROM. These eight outputs from the Master

must also drive the address inputs on the slave devices.

LOAD LAST

MASTER

COEFFICIENT

SCLK

A7:0

CCS

C15:12

0000

0001

0010

LOAD SLAVE 1

CONTROL

LOAD SLAVE 1

COEFFICIENTS

LOAD LAST

SLAVE 1

COEFFICIENT

LOAD SLAVE 2

CONTROL

LOAD SLAVE 2

COEFFICIENTS

Fig. 15a EPROM load sequence

Fig. 15b EPROM load sequence for a cascaded system

SCLK

LOAD MASTER CONTROL

LOAD LAST COEFFICIENT

A7:0

LOAD FIRST COEFFICIENT

VALID ADDR

CCS

RES

BUSY

Fig. 15 EPROM load sequence timing diagrams

PDSP16256A Datasheet(PDF) 12 Page - Mitel Networks Corporation

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