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ST7FOXK2 Datasheet(PDF) 43 Page - STMicroelectronics |
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ST7FOXK2 Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 226 page  ST7FOXF1, ST7FOXK1, ST7FOXK2 Supply, reset and clock management 43/226 6.3.5 Internal watchdog reset The Reset sequence generated by an internal watchdog counter overflow is shown in Figure 15: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 15. Reset sequences tw(RSTL)out RUN RUN WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH ACTIVE PHASE VDD RUN RESET PIN EXTERNAL WATCHDOG ACTIVE PHASE VIT+(LVD) VIT-(LVD) th(RSTL)in RUN WATCHDOG UNDERFLOW RESET RESET SOURCE EXTERNAL RESET LVD RESET ACTIVE PHASE |
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