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X9317 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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X9317 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 14 page ![]() FN8183 Rev.10.01 Page 1 of 13 Mar 22, 2024 © 2004-2024 Renesas Electronics X9317 Low Noise, Low Power, 100 Taps, Digitally Controlled Potentiometer (XDCP™) DATASHEET The X9317 is a digitally controlled potentiometer (XDCP™). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. Applications •LCD bias control • DC bias adjustment • Gain and offset trim • Laser diode bias control • Voltage regulator output control Features • Solid-state potentiometer • 3-wire serial up/down interface • 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 99 resistive elements - Temperature compensated - End-to-end resistance range ±20% •Low power CMOS -VCC = 2.7V to 5.5V, and 5V ±10% - Standby current <5µA • High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years •RTOTAL values = 10kΩ, 50kΩ •Packages - 8 Ld SOIC, TSSOP, and MSOP • Pb-free (RoHS compliant) UP/DOWN COUNTER 7-BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF ONE DECODER RESISTOR ARRAY RH U/D INC CS WIPER SWITCHES HUNDRED VCC VSS RL RW CONTROL AND MEMORY UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) VCC (SUPPLY VOLTAGE) VSS (GROUND) RH RW RL GENERAL DETAILED 0 1 2 96 97 98 99 FIGURE 1. BLOCK DIAGRAM |
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