M41ST85Y datasheet(18/34 Pages) STMICROELECTRONICS

18 / 34 page

M41ST85Y, M41ST85W

18/34

Figure 18. Back-Up Mode Alarm Waveform

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 09h.

Bits BMB4-BMB0 store a binary multiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00=1/16 second, 01=1/4 second, 10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For

example: writing 00001110 in the Watchdog Reg-

ister = 3*1 or 3 seconds).

Note: The accuracy of the timer is within ± the se-

lected resolution.

If the processor does not reset the timer within the

specified period, the M41ST85Y/W sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset.

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit (WDS). When set to

a '0,' the watchdog will activate the IRQ/FT/OUT

pin when timed-out. When WDS is set to a '1,' the

watchdog will output a negative pulse on the RST

pin for trec. The Watchdog register, FT, AFE, ABE

and SQWE Bits will reset to a '0' at the end of a

Watchdog time-out when the WDS Bit is set to a

'1.'

The watchdog timer can be reset by two methods:

1) a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or 2) the

microprocessor can perform a WRITE of the

Watchdog Register. The time-out period then

starts over.

Note: The WDI pin should be tied to VSS if not

used.

In order to perform a software reset of the watch-

dog timer, the original time-out period can be writ-

ten

into

the

Watchdog

effectively

restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT/OUT pin. This will also

disable the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

0Fh).

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT/OUT pin and the frequency test func-

tion is activated, the watchdog function prevails

and the frequency test function is denied.

AI03920

VCC

IRQ/FT/OUT

VPFD

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

trec

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