M48T128V datasheet(6/22 Pages) STMICROELECTRONICS

6 / 22 page

M48T128Y, M48T128V*

6/22

OPERATION MODES

Figure 4., page 5 illustrates the static memory ar-

ray and the quartz controlled clock oscillator. The

clock locations contain the year, month, date, day,

hour, minute, and second in 24 hour BCD format.

Corrections for 28, 29 (leap year - valid until 2100),

30, and 31 day months are made automatically.

Byte 1FFF8h is the clock control register. This byte

controls user access to the clock information and

also stores the clock calibration setting. The seven

clock bytes (1FFFFh - 1FFF8h) are not the actual

clock counters, they are memory locations consist-

ing of BiPORT™ READ/WRITE memory cells

within the static RAM array. The M48T128Y/V in-

cludes a clock control circuit which updates the

clock bytes with current information once per sec-

ond. The information can be accessed by the user

in the same manner as any other location in the

static memory array. The M48T128Y/V also has its

own Power-Fail Detect circuit. This control circuitry

constantly monitors the supply voltage for an out

of tolerance condition. When VCC is out of toler-

ance, the circuit write protects the TIMEKEEPER®

security in the midst of unpredictable system oper-

ation. As VCC falls below the Battery Back-up

Switchover Voltage (VSO), the control circuitry au-

tomatically switches to the battery, maintaining

data and clock operation until valid power is re-

stored.

Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

1. See Table 11., page 18 for details.

Mode

VCC

DQ0-DQ7

Power

Deselect

4.5 to 5.5V

3.0 to 3.6V

VIH

High Z

Standby

WRITE

VIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

High Z

CMOS Standby

Deselect

≤ VSO(1)

High Z

Battery Back-up Mode

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