M48T58 datasheet(12/17 Pages) STMICROELECTRONICS

12 / 17 page

Two methods are available for ascertaining how

much calibration a given M48T58/58Y may require.

The first involves simply setting the clock, letting it

run for a month and comparing it to a known

accurate reference (like WWV broadcasts). While

that may seem crude, it allows the designer to give

the end user the ability to calibrate his clock as his

environment may require, even after the final prod-

uct is packaged in a non-user serviceable enclo-

sure. All the designer has to do is provide a simple

utility that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) bit, the seventh-most significant bit in the Day

at 32,768 Hz, the Frequency Test (Pin 1) will toggle

at 512 Hz. Any deviation from 512 Hz indicates the

degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 ppm oscillator

frequency error, requiring a -10 (WR001010) to be

loaded into the Calibration Byte for correction. Note

that setting or changing the Calibration Byte does

not affect the Frequency test output frequency.

The FT bit must be set using the same method used

to set the clock, using the Write bit.

The Frequency Test pin is an open drain output

which requires a pull-up resistor for proper opera-

tion. A 500-10k

Ω resistor is recommended in order

to control the rise time.

For more information on calibration, see the Appli-

cation Note AN934 "TIMEKEEPER Calibration".

POWER SUPPLY DECOUPLING and UNDER-

SHOOT PROTECTION

ICC transients, including those produced by output

switching, can produce voltage fluctuations, result-

ing in spikes on the VCC bus. These transients can

be reduced if capacitors are used to store energy,

which stabilizes the VCC bus. The energy stored in

the bypass capacitors will be released as low going

spikes are generated or energy will be absorbed

when overshoots occur. A ceramic bypass capaci-

tor value of 0.1

µF (as shown in Figure 11) is rec-

ommended in order to provide the needed filtering.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate

negative voltage spikes on VCC that drive it to

values below VSS by as much as one Volt. These

negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect

from these voltage spikes, it is recommeded to

connect a schottky diode from VCC to VSS (cathode

connected to VCC, anode to VSS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

CLOCK OPERATIONS (cont’d)

AI02169

VCC

0.1

µF

DEVICE

VCC

VSS

Figure 11. Supply Voltage Protection

12/17

M48T58, M48T58Y

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