ICS9FG104E datasheet(10/19 Pages) RENESAS

10 / 19 page

ICS9FG104E

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA

IDT®

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA

ICS9FG104E

REV D 102912

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Pin #

Name

Control Function

Type

Default

Bit 7

M/N_Enable

M/N Prog. Enable

Disable

Enable

Bit 6

Bit 5

REFOUT_En

REFOUT Enable

Disable

Enable

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: PLL Frequency Control Register

Pin #

Name

Control Function

Type

Default

Bit 7

PLL N Div8

N Divider Prog bit 8

Bit 6

PLL N Div9

N Divider Prog bit 9

Bit 5

PLL M Div5

Bit 4

PLL M Div4

Bit 3

PLL M Div3

Bit 2

PLL M Div2

Bit 1

PLL M Div1

Bit 0

PLL M Div0

Byte 10

The decimal representation

of M and N Divider in Byte

11 and 12 will configure the

PLL VCO frequency. Default

at power up = latch-in or

Byte 0 Rom table. VCO

Frequency = fXTAL x

[NDiv(9:0)+8] / [MDiv(5:0)+2]

M Divider Programming

bit (5:0)

Reserved

Byte 9

Byte 8

Byte 7

Reserved

ICS9FG104E Datasheet(PDF) 10 Page - Renesas Technology Corp

ICS9FG104E Datasheet(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL