COP8TAB9 datasheet(39/59 Pages) NSC

39 / 59 page

15.0 WATCHDOG/Clock Monitor

(Continued)

•

The CLOCK MONITOR detector circuit is active during

both the HALT and IDLE modes. Consequently, the de-

vice inadvertently entering the HALT mode will be de-

tected as a CLOCK MONITOR error (provided that the

CLOCK MONITOR enable option has been selected by

the program).

•

With the single-pin R/C oscillator option selected and the

CLKDLY bit reset, the WATCHDOG service window will

resume following HALT mode from where it left off before

entering the HALT mode.

•

With the crystal oscillator option selected, or with the

single-pin R/C oscillator option selected and the CLKDLY

bit set, the WATCHDOG service window will be set to its

selected value from WDSVR following HALT. Conse-

quently, the WATCHDOG should not be serviced for at

least 256 instruction cycles following HALT, but must be

serviced within the selected window to avoid a WATCH-

DOG error.

•

The IDLE timer T0 is not initialized with external RESET.

•

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the twelfth bit of the

IDLE counter toggles (every 4096 instruction cycles). The

user is responsible for resetting the T0PND flag.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 256 instruction

cycles following IDLE, but must be serviced within the

selected window to avoid a WATCHDOG error.

•

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the ini-

tial 256 instruction cycles without causing a WATCHDOG

error.

•

In order to RESET the device on the occurrence of a

WATCH event, the user must connect the WDOUT pin

(G1) pin to the RESET external to the device. The weak

pull-up on the WDOUT pin is sufficient to provide the

RESET connection to V

CC for devices which use both

Power On Reset and WATCHDOG.

15.4 DETECTION OF ILLEGAL CONDITIONS

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

Reading of undefined ROM gets zeroes. The opcode for

software interrupt is 00. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

The subroutine stack grows down for each call (jump to

subroutine), interrupt, or PUSH, and grows up for each

return or POP. The stack pointer is initialized to RAM location

06F Hex during reset. Consequently, if there are more re-

turns than calls, the stack pointer will point to addresses 070

and 071 Hex (which are undefined RAM). Undefined RAM

from addresses 070 to 07F (Segment 0), and all other seg-

ments (i.e., Segments 4 … etc.) is read as all 1’s, which in

turn will cause the program to return to address 7FFF Hex.

This is an undefined ROM location and the instruction

fetched (all 0’s) from this location will generate a software

interrupt signaling an illegal condition.

Thus, the chip can detect the following illegal conditions:

Executing from undefined ROM

Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

16.0 MICROWIRE/PLUS

MICROWIRE/PLUS is a serial SPI compatible synchronous

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with MICROWIRE/PLUS

or SPI peripherals (i.e. A/D converters, display drivers, EE-

PROMs etc.) and with other microcontrollers which support

the MICROWIRE/PLUS or SPI interface. It consists of an

8-bit serial shift register (SIO) with serial data input (SI),

serial data output (SO) and serial shift clock (SK). Figure 29

shows a block diagram of the MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS

arrangement with the internal clock source is called the

Master

mode

operation.

Similarly,

operating

the

MICROWIRE/PLUS arrangement with an external shift clock

is called the Slave mode of operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the

master mode, the SK clock rate is selected by the two bits,

SL0 and SL1, in the CNTRL register. Table 18 details the

different clock rates that may be selected.

TABLE 18. MICROWIRE/PLUS

Master Mode Clock Select

SL1

SL0

SK Period

2xt

4xt

8xt

Where tC is the instruction cycle clock

16.1 MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 29 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

WARNING

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

Setting the BUSY flag when the input SK clock is in the

active phase while in the MICROWIRE/PLUS is in the slave

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