specified by the 15 Address Inputs defines which

one of the 32,768 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

address input signal is stable, providing that the E

and G (Output Enable) access times are also sat-

isfied. If the E and G access times are not met, valid

data will be available after the later of Chip Enable

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activated

puts are changed while E and G remain low, output

Time) but will go indeterminate until the next Ad-

dress Access.

WRITE MODE

The M48Z30/30Yis in the Write Mode whenever W

and E are active. The start of a write is referenced

from the latter occurring falling edge of W or E.

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

AC MEASUREMENT CONDITIONS

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 3. Block Diagram

3/12

M48Z30, M48Z30Y