M48Z512A, M48Z512AY

8/17

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

Note: Write Enable (W) = High.

AI01221

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A18

E

G

DQ0-DQ7

VALID

READ MODE

The M48Z512A/512AY is in the Read Mode when-

ever W (Write Enable) is high and E (Chip Enable)

is low. The device architecture allows ripple-

through access of data from eight of 4,194,304 lo-

cations in the static storage array. Thus, the

unique address specified by the 19 Address Inputs

defines which one of the 524,288 bytes of data is

to be accessed. Valid data will be available at the

after the last address input signal is stable, provid-

ing that the E (Chip Enable) and G (Output En-

able) access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the later of Chip Enable Access

signals is controlled by E and G. If the outputs are

dress Inputs are changed while E and G remain

low, output data will remain valid for Output Data

next Address Access.