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PRELIMINARY DATA

September 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50LPW041

4 Mbit (512Kb x8, Uniform Block)

3V Supply Low Pin Count Flash Memory

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SUPPLY VOLTAGE

Read Operations

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LOW PIN COUNT (LPC)

– Standard Interface for embedded operation

with PC Chipsets that are without automap-

ping memory features

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ADDRESS/ADDRESS MULTIPLEXED

– A/A Mux Interface for programming equip-

ment compatibility

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LOW PIN COUNT (LPC) HARDWARE

INTERFACE MODE

– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection

– Register Based Read and Write Protection

– 5 Additional General Purpose Inputs for plat-

form design flexibility

– Synchronized with 33MHz PCI clock

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BYTE PROGRAMMING TIME

– Single Byte Mode: 10µs (typical)

– Quadruple Byte Mode: 2.5µs (typical)

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8 UNIFORM 64 Kbyte MEMORY BLOCKS

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PROGRAM/ERASE CONTROLLER

– Embedded Byte Program and Block/Chip

Erase algorithms

– Status Register Bits

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PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend

– Program other Blocks during Erase Suspend

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FOR USE in PC BIOS APPLICATIONS

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ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 3Ch

Figure 1. Logic Diagram (LPC Interface)

AI05785

4

LFRAME

LAD0-

LAD3

VCC

M50LPW041

CLK

VSS

4

IC

RP

TBL

5

INIT

WP

ID0-ID3

GPI0-

GPI4

VPP

PLCC32 (K)

TSOP40 (N)

10 x 20mm