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ST72361 Datasheet(PDF) 52 Page - STMicroelectronics |
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ST72361 Datasheet(HTML) 52 Page - STMicroelectronics |
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52 / 224 page ![]() ST72361 52/224 10 ON-CHIP PERIPHERALS 10.1 WINDOW WATCHDOG (WWDG) 10.1.1 Introduction The Window Watchdog is used to detect the oc- currence of a software fault, usually generated by external interference or by unforeseen logical con- ditions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also gener- ated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited win- dow. 10.1.2 Main Features ■ Programmable free-running downcounter ■ Conditional reset – Reset (if watchdog activated) when the down- counter value becomes less than 40h – Reset (if watchdog activated) if the down- counter is reloaded outside the window (see Figure 37) ■ Hardware/Software Watchdog activation (selectable by option byte) ■ Optional reset on HALT instruction (configurable by option byte) 10.1.3 Functional Description The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout pe- riod can be programmed by the user in 64 incre- ments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 becomes cleared), it ini- tiates a reset cycle pulling low the reset pin for typ- ically 30 µs. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. Figure 34. Watchdog Block Diagram RESET WDGA 6-BIT DOWNCOUNTER (CNT) T6 T0 WATCHDOG CONTROL REGISTER (WDGCR) T1 T2 T3 T4 T5 - W6 W0 WATCHDOG WINDOW REGISTER (WDGWR) W1 W2 W3 W4 W5 comparator T6:0 > W6:0 CMP = 1 when Write WDGCR WDG PRESCALER DIV 4 fOSC2 12-BIT MCC RTC COUNTER MSB LSB DIV 64 0 5 6 11 MCC/RTC TB[1:0] bits (MCCSR Register) |
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