Reference Only / Allayer Confidential
AL3000
Advance Information
IP Frame Routing Processor
Figure 1
System Block Diagram
•
Provides routing functions to Allayer’s RoX-II
bus Ethernet Switching devices
•
Supports up to 32 Fast Ethernet or dual Gigabit
ports on the RoX-II bus
•
High performance Network (Layer 3) and
Transport (Layer 4) address look-up engine
•
Layer 2-, 3-, or 4-flow packet classification
•
Programmable key search based on MAC and IP
source and destination address, TCP socket,
UDP socket or IP protocol number
•
Supports up to 131,072 individual host route
entries
•
Supports 802.1q priority schemes and provides
four Quality of Service (QoS) queues
•
Provides Network Address Translation (NAT)
per route database entry
•
Provides support for IP Proxy Services with re-
mappng of Layer 4 Socket replacements
•
Programmable entry aging via internal timers
and via external real-time clock
•
Re-assigns VLAN tag and priority for each
routed frame
•
Programmable replacement of MAC and/or IP
fields with associated Layer 3 and Layer 4
check-sum recalculation
•
Supports 802.3ad port aggregation
•
Supports virtually unlimited physical inter-
faces and as many logical interfaces as soft-
ware is capable
•
Congestion control for each physical interface
and the overall routing engine
•
Packet bandwidth control for each Layer 3 or
Layer 4 flow
•
Layer 3 buffer pool of up to 1024 frames
•
Provides Ethernet, Bridge, and RMON MIB
support for RoX II bus devices
•
Six high-speed DMA engines
•
0.25 micron, 2.5V / 3.3V CMOS technology
•
456-pin BGA package
SGRAM Interface
SGRAM Interface
Processor
Interface/
DMA Control
Command
Interpreter
Search
Engine
Management
DMA Host
Engine
Parser / Result
Engine
I/O Packet
Engines
Memory &
Queue
Server
RoX II
Interface
RoX II
Ring Control
Output
Queue/
RAM Control
SGRAM 4-8 MB
SGRAM 2 MB
Scan/Test
Reset
CLK
GND
3.3 Volts
32-bit uP
Bus
Search Memory
Packet Memory
48
80
20
4
48
5
Interface to Switch Device
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