COM200221 datasheet(22/82 Pages) SMSC

Part #	COM200221

Description	10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

PDF	82 Pages

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Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

Revision 09-27-07

Page 22

SMSC COM20022I

DATASHEET

Figure 5.4 -

Programmable Burst Mode DMA Transfer (Rough Timing)

The timing of the Non-Burst mode DMA data transfer is found in the Timing Diagrams section of this data

sheet. The basic sequence of operation is as follows:

nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=1).

DREQ becomes inactive after nDACK and read/write signal become active.

DREQ becomes active after nDACK or read/write signal becomes inactive.

DREQ becomes inactive after TC and the read/write signal assert (when nDACK=0). In this case,

DREQ doesn't become active again after nDACK becomes inactive.

nDACK becomes inactive after DREQ=0 and the present cycle finishes.

Gate

Time

DREQ

(Active-High)

nDACK

(Active-Low)

Transfer term

(Counting Read/Write pulse

or counting internal timer)

Restart

Transfer

COM200221 Datasheet(PDF) 22 Page - SMSC Corporation