M54HC131

M74HC131

October 1992

3 TO 8 LINE DECODER/LATCH

B1R

(Plastic Package)

ORDER CODES :

M54HC131F1R

M74HC131M1R

M74HC131B1R

M74HC131C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS131

The M54/74HC131 is a high speed CMOS 3 TO 8

LINE DECODER/LATCH fabricated in silicon gate

C2MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

This device is a DECODER/LATCH capable of se-

lecting arbitrarily one of eight outputs by three binary

inputs A, B, and C, in this case, the selected output

is at logic ”low”.

Also, when ENABLE input G1 is set low or ENABLE

input G2 is set high, selection is inhibited regardless

of other input signals and all the outputs are at high.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

DESCRIPTION

1/12