sames

sames

SA9904A

6/12

http://www.sames.co.za

Figure 5: SPI waveforms

SPI - INTERFACE

DESCRIPTION

A serial peripheral interface bus (SPI) is a synchronous bus

used for data transfers between a micro controller and the

SA9904A. The pins DO (Serial Data Out), DI (Serial Data In),

CS (Chip Select), and SCK (Serial Clock) are used in the bus

implementation. The SA9904A is the slave device with the

micro controller being bus master. The CS input initiates and

terminates data transfers. A SCK signal (generated by the

micro controller) strobes data between the micro-controller

and the SCK pin of the SA9904A device. The DI and DO pins

are the serial data input and output pins for the SA9904A,

respectively.

REGISTER ACCESS

The SA9904A contains four 24 bit registers for each phase.

The content represents active energy, reactive energy, mains

voltage and mains frequency. The register addresses are

shown in the following table:

ID

1

2

3

4

5

6

7

8

9

10

11

12

Register

Active Phase 1

Reactive Phase 1

Voltage Phase 1

Frequency Phase 1

Active Phase 2

Reactive Phase 2

Voltage Phase 2

Frequency Phase 2

Active Phase 3

Reactive Phase 3

Voltage Phase 3

Frequency Phase 3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

A5

X

X

X

X

X

X

X

X

X

X

X

X

A4

X

X

X

X

X

X

X

X

X

X

X

X

A3

0

0

0

0

0

0

0

0

1

1

1

1

A2

0

0

0

0

1

1

1

1

0

0

0

0

A1

0

0

1

1

0

0

1

1

0

0

1

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

Header

bits

The sequence 110 (0x06) must precede the 6-bit address of

the register being accessed. When CS is HIGH, data on pin DI

is clocked into the SA9904A on the rising edge of SCK. Figure

5 shows the data clocked into DI comprising of 1 1 0 A5 A4 A3

A2 A1 A0.

Address locations A5 and A4 are included for compatibility with

future developments.

Registers may be read individually and in any order. After a

register has been read, the contents of the next register value

will be shifted out on the DO pin with every SCK clock cycle.

Data output on DO will continue until CS is inactive.

The 9 bits needed for register addressing can be padded with

leading zeros when the micro-controller requires a 8 bit SPI

word length. The following sequence is valid:

0000 0001 10A5A4

A3A2A1A0

1

1

A5

A0

A1

A2

A3

A4

0

D23

D22

D21

D1

D0

D23

D22

D1

D0

DO

DI

SCK

CS

Read command

Register address

Register Data

Next data register

High impedance

0