LCD Panel Timing Controller (15")
CS5843
BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES (continued)
FEATURES
USA:
1485 Saratoga Ave. #200
San Jose, CA, 95129
Tel: 408-973-8388 Fax: 408-973-9388
Sales@myson.com.tw
www.myson.com.tw
Rev.0.91 June 2002
page 1 of 25
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
• CS5843 Interface (5V/3.3V[CMOS] input,
3.3V[CMOS] output)
• Single (XGA2: 65MHz)/dual (XGA: 32.5MHz) 6-bit
Data input; dual port 6-bit output; SXGA auto
detective
• Timing adjustable for horizontal clock output
• Correspondent to control timing & specific resolu-
tion for different Driver IC by changing a Mask:
1. can vary the pulse width & starting position
of LP signal and POL signal polarity
position changed along with LP signal
2. can vary the pulse width & starting position
of CLKV signal and tgs time
• Control ASIC output timing design is based on
Data Enable signals
• Embedded Power On Reset circuits, Vth=2.1V, tol-
erance ± 0.3V
•
ESD spec. 4KV
•
Power On Latch Up 200mA/6.6V
• Single 3.3V supply
• 144-pin LQFP package
The CS5843 is a TFT-LCD timing controller, which
is applicable to 6-bit data XGA (1024*768), SXGA
(1280*1024).
CS5843 can update the response timing for
display mode of XGA and SXGA automatically.
CS5843 provides a selectable polarity check
function to inverse output data for EMI reducing,
when the toggle number of ODD/EVEN RGB outputs
is larger than 10.
DENA
VD
HD
DCLK1
INV
PNDCLK
PNVD
POLIN
DATAHT
SXMD
PNHMS
PLMD
SET
HITAENB
CLKHT
GT(2~1)
ODDRI(5~0)
ODDGI(5~0)
ODDBI(5~0)
PNHD
ICMD(2~1)
SCMD
EVENRI(5~0)
EVENGI(5~0)
EVENBI(5~0)
CLKV
STV1
STV2
CLKH
STH8
POL
RLSC
LP
SHC
STH1
POWER ON RESET
POL/SHC
GENERATOR
CLKV
GENERATOR
LP
GENERATOR
CLKH
GENERATOR
DELAY
SAMPLE
POLARITY
OUTPUT
SELECTOR
DATA-PATH
ODDGO(5~0)
EVENGO(5~0)
ODDRO(5~0)
EVENRO(5~0)
ODDBO(5~0)
EVENBO(5~0)
HMS1
STH1/STH8
GENERATOR
STV1/STV3
GENERATOR
RGBD
INPUT
SELECTOR
HMS2
CS5843
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