M54HC76

M74HC76

October 1992

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

B1R

(Plastic Package)

ORDER CODES :

M54HC76F1R

M74HC76M1R

M74HC76B1R

M74HC76C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

.

HIGH SPEED

.

LOW POWER DISSIPATION

µA (MAX.) AT 25 °C

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

HIGH NOISE IMMUNITY

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS76

The M54/74HC76 is a high speed CMOS DUAL J-K

FLIP FLOP fabricated in silicon gate C

nology. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. Depending on with the logic level at the J

and K inputs this device changes state on the nega-

tive going transition of the clock pulse. CLEAR and

PRESET are independent of the clock and are ac-

complished by a logic low on the corresponding

input. All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

DESCRIPTION

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