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LAN9312 Datasheet(PDF) 347 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 347 Page - SMSC Corporation |
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347 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 347 Revision 1.2 (04-08-08) DATASHEET 14.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) This register provides a counter deferred packets. The counter is cleared upon being read. Register #: Port0: 0451h Size: 32 bits Port1: 0851h Port2: 0C51h BITS DESCRIPTION TYPE DEFAULT 31:0 TX Deferred Count of packets that were available for transmission but were deferred on the first transmit attempt due to network traffic (either on receive or prior transmission). This counter is not incremented on collisions. This counter is incremented only in half-duplex operation. Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. RC 00000000h |
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