LAN9312 datasheet(412/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

412

SMSC LAN9312

DATASHEET

14.5.4

Buffer Manager CSRs

This section details the Buffer Manager (BM) registers. These registers allow configuration and

monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their

corresponding register numbers is included in Table 14.12.

14.5.4.1

Buffer Manager Configuration Register (BM_CFG)

This register enables egress rate pacing and ingress rate discarding.

1C00h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:7

RESERVED

BM Counter Test

When this bit is set, Buffer Manager (BM) counters that normally clear to 0

when read, will be set to 7FFF_FFFC when read.

R/W

Fixed Priority Queue Servicing

When set, output queues are serviced with a fixed priority ordering. When

cleared, output queues are serviced with a weighted round robin ordering.

R/W

4:2

Egress Rate Enable

When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch

ports 2,1,0 respectively.

R/W

Drop on Yellow

When this bit is set, packets that exceed the Ingress Committed Burst Size

(colored Yellow) are subjected to random discard.

Note:

See Section 14.5.3.26, "Switch Engine Ingress Rate Command

information on configuring the Ingress Committed Burst Size.

R/W

Drop on Red

When this bit is set, packets that exceed the Ingress Excess Burst Size

(colored Red) are discarded.

Note:

See Section 14.5.3.26, "Switch Engine Ingress Rate Command

information on configuring the Ingress Excess Burst Size.

R/W

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