4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs

Datasheet

SMSC USB2226

15

Revision 1.4 (10-08-07)

DATASHEET

CF_nPWR

105

I/O8

CF Card Power Control:

This active low output is intended to drive an external power control

P-FET which will supply the CF card with power.

SM/xD_PWR

79

I/O8

SM / xD Card Power drive of 3.3V @ 100mA.

SD/MMC_PWR

44

I/O8

SD / MMC Card Power drive of 3.3V @ 200mA.

CLK_SEL[1:0]

92

93

I/O8

Clock Select:

These pins will select the maximum clock rate that the interface will

operate at.

nRESET

115

IS

RESET input:

This active low signal is used by the system to reset the chip. The

active low pulse should be at least 1

μs wide.

nTEST[1:0]

95

96

I

TEST input:

These signals are used for testing the chip. User should normally tie

them high externally, if the test function is not used.

DIGITAL POWER, GROUNDS, and NO CONNECTS

VDD18

49

106

1.8v Digital Core Power:

+1.8V Core power

All VDD18 pins must be connected together on the circuit board.

VDD33

3

43

80

100

108

109

3.3v Power & Voltage Regulator Input:

3.3V Power & Regulator Input.

pins 100 & 108 supply 3.3V power to the internal 1.8V regulators.

VSS

15

16

47

84

85

97

112

Ground:

Ground Reference

SYMBOL

128-PIN

VTQFP

BUFFER

TYPE

DESCRIPTION

Table 5.1 CLK_SEL[1:0] Assignments

CLK_SEL1

CLK_SEL0

CLOCK RATE

X

1

SD/MMC and MS max clock

is 15Mhz

0

0

SD/MMC max clock is 48Mhz;

MS clock is set normally

1

0

SD/MMC max clock is 24Mhz;

MS clock is set normally