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PRELIMINARY DATA

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M59BW102

1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory

s

2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM,

ERASE and READ OPERATIONS

s

SEQUENTIAL CYCLE TIME: 25ns

s

RANDOM ACCESS TIME

s

PROGRAMMING TIME: 10µs typical

s

INTERLEAVED ACCESS TIME: 16ns

s

CONTINUOUS MEMORY INTERLEAVING

– Unlimited Linear Access Data Output

s

PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Word-by-Word

– Status Register bits

s

LOW POWER CONSUMPTION

– Stand-by and Automatic Stand-by

s

100,000 PROGRAM/ERASE CYCLES

s

20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

s

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: C1h

DESCRIPTION

The M59BW102 is a non-volatile memory that may

be erased electrically at the chip level and pro-

grammed in-system on a Word-by-Word basis us-

Erase operations the necessary high voltages are

generated internally. The device can also be pro-

grammed in standard programmers.

The device can be programmed and erased over

100,000 cycles.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature, Programming and

Chip Erase are written to the device in cycles of

commands to a Command Interface using stan-

dard

microprocessor

write

timings.

The

M59BW102 features an interleaved access mo-

dality which allows extremely fast access time.

The device is offered in TSOP40 (10 x 14mm)

package.

Figure 1. Logic Diagram

AI02763B

16

A0-A15

W

DQ0-DQ15

VCC

M59BW102

E

VSS

16

G

ALE

TSOP40 (N)

10 x 14mm