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M59DR016C, M59DR016D

Table 17. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

Parameter

M59DR016

Unit

Min

Typ

Typical after

100k W/E Cycles

Parameter Block (4 KWord) Erase (Preprogrammed)

2.5

0.15

0.4

s

Main Block (32 KWord) Erase (Preprogrammed)

10

1

3

s

Bank Erase (Preprogrammed, Bank A)

2

6

s

Bank Erase (Preprogrammed, Bank B)

10

30

s

20

25

s

(2)

10

s

200

10

10

µs

Double Word Program

200

10

10

µs

Program/Erase Cycles (per Block)

100,000

cycles

POWER CONSUMPTION

Power Down

The memory provides Reset/Power Down control

input RP. The Power Down function can be acti-

vated only if the relevant Configuration Register bit

is set to ’1’. In this case, when the RP signal is

the outputs are in high impedance.If RP is pulled

content is no longer valid (see Reset/Power Down

input description).

Power Up

The memory Command Interface is reset on Pow-

er Up to Read Array. Either E or W must be tied to

and the possibility to write a command on the first

rising edge of W.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

trace widths should be sufficient to carry the re-