M616Z08 datasheet(10/14 Pages) STMICROELECTRONICS

10 / 14 page

M616Z08

10/14

“Operational” Mode

The M616Z08 has a Chip Enable power down fea-

ture which invokes an automatic standby mode

whenever Chip Enable is de-asserted (CE =High).

An Output Enable (OE) signal provides a high

speed tri-state control, allowing fast READ/WRITE

cycles to be achieved with the common I/O data

bus. Operational modes are determined by device

control inputs WE0 or WE1 and CE as summa-

rized in “Operating Modes” (see Table 8 and Table

9).

Noise Immunity

When designing with high speed memory, proper

power trace layout and capacitive decoupling

must be maintained to ensure proper system oper-

ation. Power and ground line inductance should be

reduced by providing separate power planes. The

impedance of the decoupling path from the power

pin through the decoupling capacitor should also

be kept to a minimum. Small decoupling capaci-

tors (10nF) should be located as close to the de-

vice pins as possible to limit the high frequency

noise. Larger capacitor values (10uF and 1uF) are

recommended to reduce low frequency noise and

should be placed next to the power entry point of

the board. Proper line termination should also be

employed to minimize signal reflection.

See Motorola Semiconductor Application Note

AN2127/D for additional Electromagnetic Compat-

ibility (EMC) system design guidelines.

Table 8. WE(0,1) States during Access

Table 9. Operating Modes

Note: 1. X = '1' or '0'

WRITE Enable

Used during 16-bit Port Access

WE0

WRITE Enable for DQ (0-7)

WE1

WRITE Enable for DQ (8-15)

Operation

WE0

WE1

DQ0–DQ7

DQ8–15

Deselect

VIH

X(1)

Hi-Z

Word WRITE

VIL

VIH

VIL

Hi-Z

Byte 0 WRITE

VIL

VIH

VIL

VIH

Hi-Z

Byte 1 WRITE

VIL

VIH

VIL

Hi-Z

Byte 0 WRITE, Byte 1 READ

VIL

VIH

Hi-Z

Data

Byte 1 WRITE, Byte 0 READ

VIL

VIH

VIL

Data

Hi-Z

Word READ

VIL

VIH

Data

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