RTL8181
CONFIDENTIAL
v1.0
39
Bit
Bit Name
Description
R/W
7:5
-
Reserved
4
RST
Reset: Setting this bit to 1 forces the RTL8181 do the WLAN MAC reset. During reset
reset state, it will disable the transmitter and receiver, and reinitializes the FIFOs. The
values of WLAN_IDR and WLAN_MAR7 will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 when the reset operation is complete.
R/W
3
RE
Receiver Enable: When set to 1, and the receive state machine is idle, the receive machine
becomes active. This bit will read back as 1 whenever the receive state machine is active.
After initial power- up, software must insure that the receiver has completely reset before
setting this bit.
1: Enable
0: Disable
R/W
2
TE
Transmitter Enable: When set to 1, and the transmit state machine is idle, the transmit state
machine becomes active. This bit will read back as 1 whenever the transmit state machine
is active. After initial power-up, software must insure that the transmitter has completely
reset before setting this bit.
1: Enable
0: Disable
R/W
1-0
-
Reserved
Interrupt Mask Register (WLAN_IMR)
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset will clear all mask
bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to cause an interrupt. The Interrupt Status
Register bits are always set to 1 if the condition is present, regardless of the state of the corresponding mask bit.
Bit
Bit Name
Description
R/W
15
TXFOVW
Tx FIFO Overflow Interrupt:
1: Enable
0: Disable
R/W
14
TimeOut
Time Out Interrupt:
1: Enable
0: Disable
R/W
13
BcnInt
Beacon Time out Interrupt:
1: Enable
0: Disable
R/W
12
ATIMInt
ATIM Time Out Interrupt:
1: Enable
0: Disable
R/W
11
TBDER
Tx Beacon Descriptor Error Interrupt:
1: Enable
0: Disable
R/W
10
TBDOK
Tx Beacon Descriptor OK Interrupt:
1: Enable
0: Disable
R/W
9
THPDER
Tx High Priority Descriptor Error Interrupt:
1: Enable
0: Disable
R/W
8
THPDOK
Tx High Priority Descriptor OK Interrupt:
1: Enable
0: Disable
R/W
7
TNPDER
Tx Normal Priority Descriptor Error Interrupt:
1: Enable
0: Disable
R/W
6
TNPDOK
Tx Normal Priority Descriptor OK Interrupt:
1: Enable
0: Disable
R/W
5
RXFOVW
Rx FIFO Overflow Interrupt:
1: Enable
0: Disable
R/W
4
RDU
Rx Descriptor Unavailable Interrupt:
R/W
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