M7040N datasheet(148/159 Pages) STMICROELECTRONICS

148 / 159 page

M7040N

148/159

JTAG (1149.1) TESTING

The M7040N supports the Test Access Port and

Boundary Scan Architecture as specified in the

IEEE JTAG standard 1149.1. The pin interface to

the chip consists of five signals with the standard

definitions: TCK, TMS, TDI, TDO, and TRST_L.

Table 53 describes the operations that the test ac-

cess port controller supports and Table 54 de-

scribes the TAP Device ID Register.

Note: To disable JTAG functionality, connect the

TCK, TMS, and TDI pins to Ground, and TRST_L

to VDD.

Table 53. Supported Operations

Table 54. TAP Device ID Register

Instruction

Type

Description

SAMPLE/PRELOAD

Mandatory

Sample/Preload. Loads the values of signals going to and from IO

pins into the boundary scan shift register to provide a snapshot of

the normal functional operation.

EXTEST

Mandatory

External Test. Uses boundary scan values shifted in from TAP to

test connectivity external to the device.

INTEST

Optional

Internal Test. Allows slow-speed, functional testing of the device

using the boundary scan register to provide the I/O values.

Field

Range

Initial Value

Description

Revision

[31:28]

0001

Revision Number. This is the current device revision number.

Numbers start from one and increment by one for each revision

of the device.

Part #

[27:12]

0000 0000 0000 0100

This is the part number for this device.

MFID

[11:1]

000_1101_1100

Manufacturer ID. This field is the same as the manufacturer ID

used in the TAP controller.

LSB

[0]

Least Significant Bit

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