MK50H27PLCC datasheet(2/56 Pages) STMICROELECTRONICS

2 / 56 page

INTRODUCTION (Continued)

and out of memory through the Host’s bus.

possible system configuration for the MK50H27 is

shown in figure 1.

For added flexibility a transparent mode provides

an HDLC transport mechanism without link layer

support. In this mode no protocol processing is

done, all data received between opening flag and

CRC is written to the shared memory buffer and it

is up to the user to take care of the upper level

software.

The MK50H27 may be used with any of several

popular microprocessors, such as: 68040 ...

68000, 6800, Z8000, Z80, 80486 ... 8086, i960,

etc.

The MK50H27 may be operated in either full or

half duplex mode. In half duplex mode, the RTS

and CTS modem control pins are provided. In full

duplex mode, these pins become user program-

mable I/O pins. All signal pins on the MK50H27

are TTL compatible. This has the advantage of

making the MK50H27 independent of the physical

interface. As shown in figure 1, line drivers and

receivers are used for electrical connection to the

physical layer.

VSS-GND

DAL07

DAL06

DAL05

DAL04

DAL03

DAL02

DAL01

DAL00

READ

INTR

DALI

DALO

DAS

BMO, BYTE, BUSREL

BMI, BUSAKO

HOLD, BUSRQ

ALE, AS

ADR

READY

RESET

VSS-GND

HLDA

TCLK

A18

A19

A20

A21

A22

A23

DSR, CTS

SYSCLK

RCLK

DTR, RTS

VCC (+5V)

DAL08

DAL09

DAL10

DAL11

DAL12

DAL13

DAL14

DAL15

A16

A17

DIP48 PIN CONNECTION (Top view)

MK50H27

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