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Links
Throughout this section a + indicates the default link position.
Default Link Position Diagram
Counter 0 Clock Frequency selection
LK1 is used to select the clock frequency for counter 0.
Timer/Counter Output Signals
LK3 & LK4 are used to route the counter/timer output signals to the 50 way I/O connector. These
signals share pins with I/O lines 16 and 17.
Note:- These signals are buffered before being sent to the links, and have the same open-collector
output stage as the other I/O signals. When these links are fitted the corresponding output line
should be set to a logic 1 i.e. OFF. If the timer/counter outputs are not required the links should not
be fitted.
Power Up Output State Control
LK10-14 are used to set the power up state of the digital I/O lines, which are to be used as outputs.
Each link is associated with a group of eight I/O lines.
Page 5
2192-09099-000-000
J591 APCI-IB40
LK1
A +
B
C
CLK 0 Input
1MHZ
100KHZ
10KHZ
LK3
Connects timer/counter channel 2 output to ribbon cable pin 24 (I/O Line 17)
Connects timer/counter channel 1 output to ribbon cable pin 23 (I/O Line 16)
LK4
Link
I/O Lines
Position A + Position B
LK10
0-7
1
0
LK11
8-15
1
0
LK12
16-23
1
0
LK13
24-31
1
0
LK14
32-39
1
0
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