ST7LITE3XF2 datasheet(141/173 Pages) STMICROELECTRONICS

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driven by external square wave, LVD disabled.

3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at

VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

5. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU

max.

7. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 77. Typical IDD in RUN vs. fCPU

Figure 78. Typical IDD in SLOW vs. fCPU

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

2.4

2.7

3.3

456

Vdd (V)

8MHz

4MHz

1MHz

0.00

200.00

400.00

600.00

800.00

1000.00

2.4

2.7

3.3

Vdd (V)

8MHz

4MHz

1MHz

ST7LITE3XF2 Datasheet(PDF) 141 Page - STMicroelectronics

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