PSD211RN datasheet(15/51 Pages) STMICROELECTRONICS

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PSD211R Family

10.0

I/O Port

Functions

The PSD211R has three I/O ports (Ports A, B, and C) that are configurable at the bit level.

This permits great flexibility and a high degree of customization for specific applications.

The next section describes the control registers for the ports. Following that are sections

that describe each port. Figures 5 through 7 show the structure of Ports A through C,

respectively.

Note: any unused inputs should be connected directly to ground or pulled up to VCC (using

a 10K

Ω to 100KΩ resistor).

10.1 CSIOPORT Registers

Control of the ports is primarily handled through the CSIOPORT registers. There are 24

bytes in the address space, starting at the base address labeled CSIOPORT. Since the

PSD211R uses internal address lines A15-A11 for decoding, the CSIOPORT space

will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved

to reduce wasted address space by connecting lower order address lines (A10 and below)

to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The

CSIOPORT space must be defined in your PSDsoft design file. The following tables list

the registers located in the CSIOPORT space.

Table 5. CSIOPORT Registers for 8-Bit Data Busses

NOTE: 1. ZPSD only.

Offset (in hex)

Type of

from CSIOPORT

Access

Base Address

Allowed

Port A Pin Register

Read

Port A Direction Register

Read/Write

Port A Data Register

Read/Write

Port B Pin Register

Read

Port B Direction Register

Read/Write

Port B Data Register

Read/Write

Power Management Register (Note 1)

+10

Read/Write

10.2 Port A (PA0-PA7)

MCU I/O Mode

The default configuration of Port A is MCU I/O. In this mode, every pin can be set

(at run-time) as an input or output by writing to the respective pin’s direction flip-flop

(DIR FF, Figure 5). As an output, the pin level can be controlled by writing to the respective

pin’s data flip-flop (DFF, Figure 5A). The Pin Register can be read to determine logic level

of the pin. The contents of the pin register indicate the true state of the PSD driving the pin

through the DFF or an external source driving the pin.

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