PSD211RM datasheet(16/51 Pages) STMICROELECTRONICS

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PSD211R

10.0

I/O Port

Functions

(Cont.)

10.2 Port A (PA0-PA7) (Cont.)

Latched Address Output Mode

Alternatively, any bit(s) of Port A can be configured to output a low-order demultiplexed

address bus bit. The address is provided by the internal PSD address latch, which latches

the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed

address bits. This feature can eliminate the need for an external latch (for example:

74LS373) if you have devices that require low-order latched address bits. Although any pin

of Port A may output an address signal, the pin is position-dependent. In other words, pin

PA0 of Port A may only pass A0, PA1 only A1, and so on.

The control registers of Port A are located in CSIOPORT space; see Table 5. Each pin of

Port A can be individually configured. The following table summarizes what the control

registers (in CSIOPORT space) for Port A do:

NOTE: 1. Default value is the value after reset.

Default

Value

0 Value

1 Value

(Note 1)

Port A Pin Register

Sampled logic level

at pin = ‘0’

at pin = ‘1’

Port A Direction Register

Pin is configured

as input

as output

Port A Data Register

Data in DFF = ‘0’

Data in DFF = ‘1’

Figure 5. Port A Pin Structure

READ PIN

PORT A PIN

ENABLE

LATCHED

ADDR

OUT

MCU

I/O

OUT

READ DATA

WRITE DATA

ALE

READ DIR

WRITE DIR

RESET

DFF

LATCH

DIR

CONTROL

MUX

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