PSD913F2 datasheet(32/94 Pages) STMICROELECTRONICS

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The

PSD9XX

Functional

Blocks

(cont.)

Level 1

SRAM, I /O

Level 2

Secondary Flash Memory

Highest Priority

Lowest Priority

Level 3

Main Flash Memory

Figure 5. Priority Level of Memory and I/O Components

9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces

The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,

80C251, 80C51XA, and the C500 family have separate address spaces for code memory

(selected using PSEN) and data memory (selected using RD). Any of the memories

within the PSD9XX can reside in either space or both spaces. This is controlled through

manipulation of the VM register that resides in the PSD’s CSIOP space.

The VM register is set using PSDsoft to have an initial value. It can subsequently be

changed by the microcontroller so that memory mapping can be changed on-the-fly.

For example, you may wish to have SRAM and Flash in Data Space at boot, and Boot

Block in Program Space at boot, and later swap Boot Block and Flash. This is easily done

with the VM register by using PSDsoft to configure it for boot up and having the microcon-

troller change it when desired.

Table 13 describes the VM Register.

Bit 7*

Bit 6*

Bit 5*

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FL_Data Boot_Data

FL_Code

Boot_Code SRAM_Code

0 = RD

0 = PSEN

can’t

access

Flash

Secondary

Flash

Secondary

SRAM

Flash

1 = RD

1 = PSEN

access

Flash

Secondary

Flash

Secondary

SRAM

Flash

Table 13. VM Register

NOTE: Bits 5-7 are not used, should set to “0”.

PSD9XX Family

Preliminary Information

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