RIVA128 datasheet(18/77 Pages) STMICROELECTRONICS

18 / 77 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA 128

18/77

Figure 5.

Basic AGP pipeline concept

Pipeline operation

Memory access pipelining provides the main per-

formance enhancement of AGP over PCI. AGP

pipelined bus transactions share most of the PCI

signal set, and are interleaved with PCI transac-

tions on the bus.

The RIVA 128 supports AGP pipelined reads with

a 4-deep queue of outstanding read requests.

Pipelined reads are primarily used by the RIVA

128 for cache filling, the cache size being opti-

mized for AGP bursts. Depending on the AGP

bridge, a bandwidth of up to 248MByte/s is achiev-

able for 128-byte pipelined reads. This compares

with around 100MByte/s for 128-byte 33MHz PCI

reads. Another feature of AGP is that for smaller

sized reads the bandwidth is not significantly re-

duced. Whereas 16-byte reads on PCI transfer at

around 33MByte/s, on AGP around 175MByte/s is

achievable. The RIVA 128 actually requests reads

greater than 64 bytes in multiples of 32-byte trans-

actions.

The pipe depth can be maintained by the AGP bus

master (RIVA 128) intervening in a pipelined trans-

fer to insert new requests between data replies.

This bus sequencing is illustrated in Figure 5.

When the bus is in an idle condition, the pipe can

be started by inserting one or more AGP access

requests consecutively. Once the data reply to

those accesses starts, that stream can be broken

(or intervened) by the bus master (RIVA 128) in-

serting one or more additional AGP access re-

quests or inserting a PCI transaction. This inter-

vention is accomplished with the bus ownership

signals, PCIREQ# and PCIGNT#.

The RIVA 128 implements both high and low prior-

ity reads depending of the status of the rendering

engine. If the pipeline is likely to stall due to sys-

tem memory read latency, a high priority read re-

quest is posted.

Address Transactions

The RIVA 128 requests permission from the

bridge to use PCIAD[31:0] to initiate either an

AGP request or a PCI transaction by asserting

PCIREQ#. The arbiter grants permission by as-

serting PCIGNT# with AGPST[2:0] equal to ‘111’

(referred to as START). When the RIVA 128 re-

ceives START it must start the bus operation with-

in two clocks of the bus becoming available. For

example, when the bus is in an idle condition when

START is received, the RIVA 128 must initiate the

bus transaction on the next clock and the one fol-

lowing.

Figure 6 shows a single address being enqueued

by the RIVA 128. Sometime before clock 1, the

RIVA 128 asserts PCIREQ# to gain permission to

use PCIAD[31:0]. The arbiter grants permission

by indicating START on clock 2. A new request

(address, command and length) are enqueued on

each clock in which AGPPIPE# is asserted. The

address of the request to be enqueued is present-

ed on PCIAD[31:3], the length on PCIAD[2:0] and

the command on PCICBE[3:0]#. In Figure 6 only

a single address is enqueued since AGPPIPE# is

just asserted for a single clock. The RIVA 128 in-

dicates that the current address is the last it in-

tends to enqueue when AGPPIPE# is asserted

and PCIREQ# is deasserted (occurring on clock

3). Once the arbiter detects the assertion of AGP-

PIPE# or PCIFRAME# it deasserts PCIGNT# on

clock 4.

Bus Idle

Pipelined

data

transfer

Intervene

cycles

Pipelined AGP requests

Data-1

Data-2

PCI transaction

Data

Data-3

RIVA128 Datasheet(PDF) 18 Page - STMicroelectronics

RIVA128 Datasheet(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL