PSD813F1V datasheet(9/120 Pages) STMICROELECTRONICS

9 / 120 page

Preliminary

PSD813F1-A

3.0

General

Information

The PSD813F1 series architecture allows In-System Programming of all Memory, PLD

Logic and Device Configuration. The embedded Input and Output Micro

⇔Cells enable

efficient implementation of user defined logic functions that require both software and

hardware interaction. The devices eliminate the need for discrete ‘glue’ logic, and allow the

development of entire systems using only a few highly integrated devices.

4.0

PSD813F1

Family

All PSD813F1 devices provide these features: 1 Mbit main Flash Memory, JTAG port,

CPLD, DPLD, power management, and 27 I/O pins. The PSD813F1 also adds 64 bytes of

OTP memory for any use (product serial number, calibration constants, etc.). Once written,

the OTP memory can never be altered.

The following table summarizes the PSD813F1:

Part #

Flash

Additional

No. of

Serial ISP

Main Memory

Memory for

PSD813F1

I/O

Micro

⇔Cells JTAG/ISC

Kbit

Boot and/or Data

SRAM

Turbo

Supply

Family

Device

Pins

Input/Output

Port

(8 Sectors)

(4 Sectors)

Kbit

Mode

Voltage

PSD813F1

24/16

Yes

1024

256 Kbit EEPROM

Yes

PSD813F1V

24/16

Yes

1024

256 Kbit EEPROM

Yes

Table 1. PSD813F1 Product Matrix

PSD813F1V Datasheet(PDF) 9 Page - STMicroelectronics

PSD813F1V Datasheet(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL