Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF9562 – 1

Pin Assignment

for LCC

TLF9562 – 2

Functional Description

The ’F563 contains eight D-type latches with TRI-STATE

output buffers When the Latch Enable (LE) input is HIGH

the latches are transparent ie a latch output will change

state each time its D input changes When LE is LOW the

latches store the information that was present on the D in-

puts a setup time preceding the HIGH-to-LOW transition of

LE The TRI-STATE buffers are controlled by the Output

Enable (OE) input When OE is LOW the buffers are in the

bi-state mode When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches

Function Table

Inputs

Internal

Output

Function

OE

LE

D

Q

O

H

X

X

X

Z

High Z

H

H

L

H

Z

High Z

H

H

H

L

Z

High Z

H

L

X

NC

Z

Latched

L

H

L

H

H

Transparent

L

H

H

L

L

Transparent

L

L

X

NC

NC

Latched

Logic Diagram

TLF9562 – 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2