Secure Microprocessor Chip

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13

Pin Description (continued)

PIN

NAME

FUNCTION

BYTE-WIDE BUS INTERFACE PINS

37

BA0

35

BA1

33

BA2

30

BA3

28

BA4

26

BA5

24

BA6

20

BA7

6

BA8

4

BA9

76

BA10

80

BA11

18

BA12

8

BA13

16

BA14

Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed data bus

(BD7–BD0) to access external SRAM. Decoding is performed using CE1–CE4. Therefore, BA15

is not actually needed. Read/write access is controlled by R/W. BA14–BA0 connect directly to

an 8kB, 32kB, or 128kB SRAM. If an 8kB SRAM is used, BA13 and BA14 are unconnected. If a

128kB SRAM is used, the microcontroller converts CE2 and CE3 to serve as A16 and A15,

respectively.

55

BD0

57

BD1

59

BD2

61

BD3

65

BD4

67

BD5

69

BD6

71

BD7

Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the nonmultiplexed

address bus (BA14–BA0) to access external SRAM. Decoding is performed on CE1 and CE2.

Read/write access is controlled by R/W. D7–D0 connect directly to an SRAM and optionally to a

real-time clock or other peripheral.

70

ALE

Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on port

0. This pin is normally connected to the clock input on a ’373 type transparent latch.

10

R/W

Read/Write (Active Low). This signal provides the write enable to the SRAMs on the byte-wide

bus. It is controlled by the memory map and partition. The blocks selected as program (ROM)

are write protected.

74

CE1

Active-Low Chip-Enable 1. This is the primary decoded chip enable for memory access on the

byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed. It

72

CE1N

Nonbattery-Backed Version of CE1. It is not generally useful because the DS5003 cannot be

used with EPROM due to its encryption.

2

CE2

Active-Low Chip-Enable 2. This chip enable is provided to access a second 32kB block of

memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller

converts CE2 into A16 for a 128kB x 8 SRAM. CE2 is lithium-backed and remains at a logic-high

63

CE3

Active-Low Chip-Enable 3. This chip enable is provided to access a third 32kB block of

memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the microcontroller

converts CE3 into A15 for a 128kB x 8 SRAM. CE3 is lithium backed and remains at a logic-high