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553S Datasheet(PDF) 2 Page - Renesas Technology Corp |
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553S Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 11 page ![]() 2 ©2015–2026 Renesas Electronics Corporation August 14, 2026 553S Datasheet Pin Assignments Pin Descriptions External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 553S is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. Pin Number Pin Name Pin Type Pin Description 1 VDD Power Connect to +1.8V, +2.5V, or +3.3V. 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 GND Power Connect to ground. 5 ICLK Input Clock input. 6 Q2 Output Clock output 2. 7 Q3 Output Clock output 3. 8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. 1 2 3 VDD 4 Q0 Q1 Q3 GND Q2 ICL K 8 7 6 5 OE 8- pi n SOI C 1 2 3 VDD 4 Q0 Q1 Q3 GND Q2 ICLK 8 7 6 5 OE 8-pin DFN |
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