13

©2019-2023 Renesas Electronics Corporation

R31DS0029EU0601 September 13, 2023

XF Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω

transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.

Figure 4 and Figure 5 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and

it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component

process variations.

Figure 4. 3.3V LVPECL Output Termination

Figure 5. 3.3V LVPECL Output Termination