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Copyright © 2013 Future Technology Devices International Limited

VMusic3

Version 1.0

Document Reference No.: FT_000738

Clearance No.: FTDI#

336

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VMusic3 Electrical Details

7.1

SPI Interface Timing

The following timing diagrams are for the VNC1L Legacy Interface mode of SPI slave.

SCLK

SS#

MOSI

MISO

Figure 7.1 – SPI

To start the data transfer process SS# needs to be set high, and remain high for the entire read cycle.

Once the read cycle completes SS# needs to be set low for at least one clock cycle to allow another data

transfer cycle to occur.

The first bit of MOSI is the R/W bit, receiving a logic high for this bit allows data to be read from the

VMusic3.The second bit is the address bit, ADD, this bit is used to select reading data from the data

register when set to logic high, or from the status register when set to logic low. During an SPI Read

cycle a package of data is transmitted from the VMusic3 on the MISO line from the time of the first clock

cycle after the SPI ADD bit, with the MSB transmitted first.

After the data has been transferred the status of MISO can be checked to determine if the data read is

new data that has not been read before, which is indicated by a transmitted logic low. Otherwise if old

data is being transmitted, which is indicated by a transmitted logic high, the read cycle needs to be

repeated to get new data.

SCLK

SS#

MOSI

MISO

Figure 7.2 – VMusic3 SPI Waveforms

To start the data transfer process SPI SS# needs to be set high, and remain high for the entire write

cycle. Once the write cycle SPI completes SS# needs to be set low for at least one clock cycle to allow

another data transfer cycle to occur. The first bit of MOSI is the R/W bit, receiving a logic low for this bit

allows data to be written to the VMusic3.