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74LVC595AD Datasheet(PDF) 11 Page - Nexperia B.V. All rights reserved |
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74LVC595AD Datasheet(HTML) 11 Page - Nexperia B.V. All rights reserved |
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11 / 20 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC595A All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 20 June 2014 11 of 20 Nexperia 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The data set-up and hold times for the serial data input (DS) Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The master reset (MR) to storage clock (STCP) set-up times 001aaf571 MR input STCP input Qn outputs tsu VM VI VI GND GND VOH VOL VM VM |
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