The SN54F299 is obsolete and no

longer supplied.

SN54F299, SN74F299

8BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH 3STATE OUTPUTS

SDFS071B − MARCH 1987 − REVISED APRIL 2004

2

POST OFFICE BOX 655303

FUNCTION TABLE

MODE

INPUTS

I/O PORTS

OUTPUTS

MODE

CLR

S1

S0

OE1†

OE2†

CLK

SL

SR

A/QA B/QB C/QC D/QD E/QE

F/QF G/QG H/QH

QA′

QH′

Clear

L

L

L

X

L

H

L

X

H

L

L

X

L

L

X

X

X

X

X

X

X

X

X

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

L

L

L

L

Hold

H

H

L

X

L

X

L

L

L

L

X

L

X

X

X

X

QA0

QA0

QB0

QB0

QC0

QC0

QD0

QD0

QE0

QE0

QF0

QF0

QG0

QG0

QH0

QH0

QA0

QA0

QH0

QH0

Shift

Right

H

H

L

L

H

H

L

L

L

L

↑

↑

X

X

H

L

H

L

QAn

QAn

QBn

QBn

QCn

QCn

QDn

QDn

QEn

QEn

QFn

QFn

QGn

QGn

H

L

QGn

QGn

Shift

Left

H

H

H

H

L

L

L

L

L

L

↑

↑

H

L

X

X

QBn

QBn

QCn

QCn

QDn

QDn

QEn

QEn

QFn

QFn

QGn

QGn

QHn

QHn

H

L

QBn

QBn

H

L

Load

H

H

H

X

X

↑

X

X

a

b

c

d

e

f

g

h

a

h

NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop

outputs are isolated from the I/O terminals.

† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation

or clearing of the register is not affected.

logic diagram (positive logic)

C1

1D

C1

1D

Six

Identical

Channels

Not

Shown‡

19

11

12

8

2

3

18

17

S0

S1

SR

(shift right

serial input)

CLK

QA′

OE1

OE2

SL

(shift left

serial input)

QH′

716

A/QA

H/QH

9

CLR

1

RR

‡ I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).