BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01161B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

NO ACK

R/W

ACK

ACK

NO ACK

R/W

NO ACK

NO ACK

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16)

Read Operation

Read operations are independent of the state of the

MODE signal. On delivery, the memory content is

set at all "1’s" (or FFh).

Current Address Read. The memory has an in-

ternal byte address counter. Each time a byte is

read, this counter is incremented. For the Current

Address Read mode, following a START condition,

the master sends a memory address with the RW

bit set to ’1’. The memory acknowledges this and

outputs the byte addressed by the internal byte

address counter. This counter is then incremented.

The master does NOT acknowledge the byte out-

put, but terminates the transfer with a STOP con-

dition.

Random Address Read. A dummy write is per-

formed to load the address into the address counter

(see Figure 11). This is followed by another START

condition from the master and the byte address

repeated with the RW bit set to ’1’. The memory

acknowledges this and outputs the byte ad-

dressed. The master does NOT acknowledge the

byte output, but terminates the transfer with a

STOP condition.

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

12/17

ST24/25C16, ST24/25W16