CAT3636 datasheet(13/16 Pages) CATALYST

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CAT3636

Doc. No. MD-5020 Rev. D

Characteristics subject to change without notice

Unused LED Channels

For applications with only four or two LEDs, unused

LED banks can be disabled via the enable register

internally and left to float.

For applications with 5 LEDs or less, unused LEDs

can also be disabled by connecting the LED pin

directly to VOUT, as shown on Figure 4. If LED pin

voltage is within 1V of VOUT, then the channel is

switched off and a 200μA test current is placed in the

channel to sense when the channel moves below

VOUT – 1V.

Figure 4. Five LED Application

Protection Mode

If an LED is disconnected, the output voltage VOUT

automatically limits at about 5.5V. This is to prevent

the output pin from exceeding its absolute maximum

rating.

If the die temperature exceeds +150°C the driver will

enter a thermal protection shutdown mode. When the

device temperature drops by about 20°C the device

will resume normal operation.

LED Selection

LEDs with forward voltages (VF) ranging from 1.3V to

5.0V may be used with the CAT3636. Selecting LEDs

with lower VF is recommended in order to improve the

efficiency by keeping the driver in 1x mode longer as

the battery voltage decreases.

For example, if a white LED with a VF of 3.3V is

selected over one with VF of 3.5V, the CAT3636 will

stay in 1x mode for lower supply voltage of 0.2V. This

helps improve the efficiency and extends battery life.

External Components

The driver requires two external 1μF ceramic

capacitors for decoupling input, output, and for the

charge pump. Both capacitors type X5R and X7R are

recommended for the LED driver application. In all

charge pump modes, the input current ripple is kept

very low by design and an input bypass capacitor of

1μF is sufficient.

In 1x mode, the device operates in linear mode and

does not introduce switching noise back onto the

supply.

Recommended Layout

In charge pump mode, the driver switches internally at

a high frequency. It is recommended to minimize trace

length to all four capacitors. A ground plane should

cover the area under the driver IC as well as the

bypass capacitors. Short connection to ground on

capacitors CIN and COUT can be implemented with

the use of multiple via. A copper area matching the

TQFN exposed pad (TAB) must be connected to the

ground plane underneath. The use of multiple via

improves the package heat dissipation.

Figure 5. Recommended Layout

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