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ST6387 Datasheet(PDF) 37 Page - STMicroelectronics |
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ST6387 Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 84 page  37/84 ST6365, ST6375, ST6385 ST6367, ST6377, ST6387 SERIAL PERIPHERAL INTERFACE (Cont’d) 4.3.2 S-BUS/I2C BUS Timing Diagrams The clock of the S-BUS/I 2C BUS of the ST638x SPI (single master only) has a fixed bus clock fre- quency of 62.5KHz. All the devices connected to the bus must be able to follow transfers with fre- quencies up to 62.5KHz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch low peri- ods. Figure 25. S-BUS Timing Diagram VA00454 03 4 1 SCL SEN (TRANSMIT) SDA (TRANSMIT) SDA pulled low by receiver if acknowledged. ^ ^ ^ ^ ^ ^ SDA pulled low by SPI Peripheral. SDA (RECEIVE) SEN (RECEIVE) SEN (START) SDA (START) ^ ^ ^ SDA pulled low by receiver if acknowledged. SEN (STOP) SDA (STOP) ^ ^ ^ SDA pulled low by receiver if acknowledge. If in receive then there will be no ACK. by the SPI. SCL SCL 2 16 A 7 5 57 A 6 12 1 4 3 0 57 A 6 12 1 4 3 0 |
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