ST72101 datasheet(23/84 Pages) STMICROELECTRONICS

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ST72101/ST72212/ST72213

3.5 MISCELLANEOUS REGISTER

The Miscellaneous register allows to select the

SLOW operating mode, the polarity of external in-

terrupt requests and to output the internal clock.

—

Read/ Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = PEI[3:2]

External Interrupt EI1 Polarity

Option.

These bits are set and cleared by software. They

determine which event on EI1 causes the exter-

nal interrupt according to Table 8.

Table 8. EI1 External Interrupt Polarity Options

Note: Any modification of one of these two bits re-

sets the interrupt request related to this interrupt

vector.

Bit 5 = MCO

Main Clock Out

This bit is set and cleared by software. When set, it

enables the output of the Internal Clock on the

PC2 I/O port.

0 - PC2 is a general purpose I/O port.

1 - MCO alternate function (fCPU is output on PC2

pin).

Bit 4:3 = PEI[1:0]

External Interrupt EI0 Polarity

Option.

These bits are set and cleared by software. They

determine which event on EI0 causes the exter-

nal interrupt according to Table 9.

Table 9. EI0 External Interrupt Polarity Options

Note: Any modification of one of these two bits re-

sets the interrupt request related to this interrupt

vector.

Bit 1:2 = Unused, always read at 0.

Warning: Software must write 1 to these bits for

compatibility with future products.

Bit 0 = SMS

Slow Mode Select

This bit is set and cleared by software.

0- Normal mode - fCPU = Oscillator frequency / 2

(Reset state)

1- Slow mode - fCPU = Oscillator frequency /32

PEI3

PEI2

MCO

PEI1

PEI0

SMS

MODE

PEI3

PEI2

Falling edge and low level

(Reset state)

Falling edge only

Rising edge only

Rising and falling edge

MODE

PEI1

PEI0

Falling edge and low level

(Reset state)

Falling edge only

Rising edge only

Rising and falling edge

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